System Validation and Debug - Guadalajara, México - Screenovate

Screenovate

Empresa verificada

Guadalajara, México

hace 3 semanas

Publicado por:

Rodrigo Fernández

Reclutador de talento para beBee

Descripción

We are the Data Products Architecture and Engineering (DPEA) group within the Data Center and Artificial Intelligence (DCAI) organization, driving Data Center and Cloud transformation through innovation, reliability and proven performance.

There are reasons Intel is the global leader and preferred provider of server technology and products.

Intel understands the needs of the modern data center and harnesses its years of experience and design expertise to deliver a broad portfolio of innovative server products, systems, and solutions to help businesses grow and be competitive in the market.

Our team is motivated with passionate engineers to the core of our heart and we are looking for more leaders and path finders.

We are seeking a Server Platform Validation and Debug engineer to join the Intel Xeon Accelerated Performance/ Scalable Performance (AP/SP) Platform Integration and Validation team.

This role as Platform Debug Engineer is responsible for working with reference and custom systems to define, coordinate, and lead the validation of server platforms that showcase Intel's futuristic datacenter products.

This position requires a combination of validation engineering and execution leadership.

A system validation/debug engineer is the critical link among the silicon, board, system, ingredient development teams, and the platform integration/validation teams, ensuring effective root cause and issue resolution.

Projects will be varied, including new reference designs for Intel Xeon SP/AP server platforms, high-volume customer designs, and unique one-off customer designs.

You can just not see the futuristic products getting unfolded but be a part of it, build it, take pride in it.

Your Responsibilities will include but not limited to:

Define, design, execute Server platform Pre-Silicon and Post-Silicon validation plans for current and future products.
Lead validation efforts to ensure quality of Server Platform and Silicon.
Lead debug efforts for issues found during Presilicon, Power-On, Postsilicon, Customer engagement to product release.
Lead crossfunctional engagement with Design, Silicon validation, IP teams, Execution/Automation teams and Program leads.
Develop and execute validation tasks, review requirements coverage, lead execution, drive debug and taskforces for issues resolution.
Developing test content to cover product requirements accordingly.
Voice of the team to represent issues found in debug at the corresponding forums.
Participating in product planning and release meetings providing input and facilitating decisions.
Provide mentorship and technical direction to distributed team of system validation engineers for program execution.
Role model for the organization and junior engineers.

Behavioral Traits Required

Selfmotivated, make decisions where and when needed.
Willing to deal with ambiguity.
Problemsolving skills.
Written and verbal communication skills.
Networking and influencing skills.
Track record of team skills and collaboration skills.
Demonstrated experience working across functions to deliver products.

Qualifications:

Requirements listed may be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

You must possess the below
minimum qualifications to be initially considered for this position:

2+ years of experience in
two or more of the following (not all are a must):
Handson technical, individual contributor in Silicon/Platform development engineering environment in CPU/logic and/or memory products.
Good knowledge in computer architecture (ISA, x86)
Experience working to integrate various system components (HW, BIOS, OS, Drivers, etc.) and validate/debug to the requirements for server platforms.
Solid experience in Linux development, C/C++, python.
Experience with chipset/processor interfaces (PCI Express, UPI, Memory, USB, SAS, etc.) and be able to interpret specifications to assist with debug and test development.\
Good knowledge and experience in device driver development (firmware development)
Test plan and test development experience.
System and/or Functional area expertise.
Intermedaite+ English level
Influencing the IP/SoC design decisions and/or pre/post

- validation methods by doing validation gap analysis.

Experience with Cloud Service Provider (CSP) and Original Equipment Manufacturer (OEM) teams.
Experience in automation and test/integration methodologies.
Experience developing validation methodologies and infrastructure solutions.
Experience in Server based technologies, Machine Learning, Microprocessor, CPU, or FPGA validation, PCIe, DRAM, I2C, SMBus, Ethernet architecture and Cloud Technologies.

Inside this Business Group:

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business a