Senior Verification Engineer - Guadalajara, México - Synopsys

Synopsys

Empresa verificada

Guadalajara, México

hace 3 semanas

Publicado por:

Rodrigo Fernández

Reclutador de talento para beBee

Descripción

49063BR

MEXICO
Guadalajara

Job Description and Requirements

We're not just a traditional EDA & IP company you're familiar with. We understand how the SoCs we help create are used, and work with our partners to deliver world beating products.
At Synopsys, we are at the heart of the innovations that change the way we work and play. Selfdriving cars. Artificial Intelligence. The Cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

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Senior Verification Engineer
In this position you will be responsible to define and implement test plan based on UVM. You will work across teams and/or different time zones and be proactive to improve testbench features with basic guidance.

We're looking for someone with strong debug capabilities to isolate and detect RTL/TB bugs providing a solution for most of the cases. Good communication skills will help to influence larger team members creating a technical development path according to their own professional development and personal goals.
Multitasking is required and be able to manage their own assignations based on priorities

Responsibilities:

Strong understanding of verification process and flow.
Join a project at any phase with mínimal disruption.
Participate as a lead and/or contributor.
Quickly adapt to a variety of different environments, methods, and standards.
Ability to create a highlevel verification plan.
Derivation of verification requirements from design requirements
Derivation of project schedule from verification requirements
Architect complex test environments.
Identification and integration of reuse
Ability to create a complex constrained random test environment.
Setup, build and run testbenches.
Develop agents for complex interfaces (protocol/retries/split transactions)
Application of direct and random methods
Application of coverage analysis (types and convergence methods)
Analyzing and debugging failures to establish rootcause.
Strong understanding of Object-Oriented Programming (classes, methods, polymorphism)

Requirements:

Bachelor's degree in electrical engineering, Computer Engineering, or Computer Science with 3+ years of experience in the verification of ASIC/FPGA devices.
Minimum 3 years of experience in UVM Methodology based verification.
Excellent knowledge of SystemVerilog hdl.
Emulation experience is a plus.
Highly skilled with industry standard simulation Synopsys VCS.
Strong understanding of typical design structures (FIFO's, pipelines, memories, state machines, etc.)
Strong algorithmic and problemsolving skills.
Good knowledge of scripting languages such as perl, phyton, ruby.
Strong understanding of standard protocols (DDR4, GDDR, HBM, AMBA will be great)
Comfortable and confident interacting with customers.
Excellent written and verbal communication skills.

Inclusion and Diversity are important to us.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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