Senior Director - Microprocessor Engineering - Guerrero - beBeePerformance

Título del trabajo: Senior Physical Design Engineer – CPU PPA Optimization

Descripción

We are currently seeking a seasoned Physical Design Engineer to spearhead our CPU Performance, Power, and Area (PPA) Optimization initiatives in Guadalajara, Mexico.

Key Responsibilities

• Leverage expertise in physical implementation of CPU blocks from RTL-to-GDSII to balance PPA trade-offs using back-end EDA tool flows.
• Develop / optimize methodologies for synthesis,
  place-and-route (PnR), clock tree synthesis (CTS),
  and timing closure with collaboration from logic design teams.

Closely collaborate with RTL designers to enhance timing,
area and power efficiency by evaluating modifications
& their impact on PPA via static timing analysis(STA)<​>,power analysis(signal integrity checks,DFT implementation).

About This Role

• This is an exceptional opportunity for a skilled Physical Design Engineer looking to take the lead in driving innovative solutions for CPU PPA optimization. The ideal candidate will have extensive experience working on similar projects and be well-versed in current industry trends and best practices.